Not applicable.
Not applicable.
The present invention relates generally to a method for reducing particulate defects on the surface of semiconductor wafers during the fabrication process. In particular, the invention relates to a method for reducing particle defects introduced during the chemical mechanical polishing or planarization (CMP) operation in the wafer fabrication process. More specifically, the invention relates to a method for preconditioning the CMP polishing pad and retaining ring with a cleaning chemistry for the purposes of particle and defect reduction.
Modern-day semiconductor devices, commonly called microchips or integrated circuits, are fabricated in xe2x80x9ccleanroomxe2x80x9d environments using a multi-step process that constructs numerous integrated circuits in the form of chips, or xe2x80x9cdie,xe2x80x9d on disc-shaped wafers. Due to the miniscule scale of circuitry on each integrated circuit, it is critical to the fabrication process that the wafers remain as clean and particle-free as possible, as even tiny particles may lead to defects that render a device inoperable, consequently lowering yield and associated profits. Critical to improving yield is raising the number of good die per wafer. To accomplish this, the semiconductor industry is moving in the direction of larger-diameter wafers and smaller die, so that more integrated circuits can be xe2x80x9csqueezedxe2x80x9d onto a single wafer. Also, more effective and efficient methods are sought for reducing particulate contamination of the wafers during the fabrication process.
Since the late 1950s, integrated circuit technology has evolved rapidly and has revolutionized virtually every industry and capacity in which integrated circuits are used. Today""s integrated circuits frequently employ hundreds of thousands or even millions of transistors and highly complex, multi-layered designs. The proliferation of electronics in general, and integrated circuits in particular, has resulted in large part from the ability to increase circuit functionality while simultaneously reducing device cost and size. An important catalyst for these improvements has been advances in semiconductor processing technologies, the various techniques used to construct circuit elementsxe2x80x94e.g., transistors, resistors and capacitorsxe2x80x94on the semiconductor substrate, as well as the necessary conducting interconnects between individual circuit elements. Improved materials, equipment and processes have allowed increasingly complex circuits with improved speed, reduced power requirements and smaller footprints.
Integrated circuits are typically constructed at the surface of a silicon wafer sliced from a single-crystal ingot, although other semiconductors such as gallium arsenide and germanium are also used. Individual circuit elements are fabricated on the wafer surface. The electrical conduction between appropriate circuit elements, and electrical isolation between other circuit elements, is then established using alternating layers of appropriately patterned conductors and insulators. The circuit elements and their interconnections are formed using a series of processing steps including ion implantation, thin film deposition, photolithography, selective etching, as well as various cleaning processes.
As die sizes shrink with newer technology, the functionality of integrated circuits is increasing, as are the number of active metal layers on each die. Integrated circuits are fabricated in layers using several complex operations, with many processes repeated as each layer is created. An inlaid or damascene interconnect scheme is typically used for forming copper metallization, wherein an insulating dielectric layer is deposited, followed by the formation of trenches and vias through patterning and etching processes. A diffusion barrier and copper seed layer are then deposited, followed by electrochemical plating of the copper to fill the trenches and vias. A chemical mechanical planarization (CMP) process is then used to remove the excessive portion of the copper and to planarize the surface of the wafer.
The slurries used in CMP are best classified by the types of layers, or films, they are intended to planarize. In semiconductor manufacturing, CMP processes are most commonly used for films comprised of silicon oxide, tungsten, copper, tantalum and titanium. CMP of copper films, for example, often employs slurries based on ammonia, which offers high copper ion solubility through ion complexation.
In addition to polishing of metallization layers, CMP processing generally also involves barrier layer and dielectric layer polishing. A barrier layer is a layer disposed between two layers that prevent one layer from contaminating the other layer and vice versa. Copper metallization schemes often employ barrier metals such as tantalum or tantalum-rich alloys between the copper and dielectric layers to minimize cross-contamination between those layers. Dielectric layers provide electrical isolation between conducting layers, and are frequently comprised of an oxide material such as silica. An integrated CMP processing technique should allow the polishing and planarization of alternating layers such as those describedxe2x80x94e.g., a layer comprising copper on a layer comprising tantalum on a layer comprising oxide.
Photolithography involves spinning a light-sensitive photoresist material onto the wafer surface. Next, using precise optical processes, individual integrated circuits are formed by repetitively exposing a pattern on a glass mask, or reticle, in a grid-like fashion onto the photoresist material. The exposed photoresist material is typically cured and developed, then dissolved areas of the photoresist are rinsed away, leaving the wafer ready for etching or implant doping. The aforementioned processes are generally repeated as each metal layer is fabricated, with some advanced microprocessors requiring seven or more metal layers.
As the number of layers fabricated on a wafer increase, planarity and cleanliness of the wafer surface become paramount, as minute features created on the wafer surface must line up with corresponding features on the layer below. Such features are often only a fraction of a micron wide (where a micron is one millionth of a meter) so it is critical that the wafer surface be substantially free of topological defects, as with every subsequent layer, any topological defect becomes magnified. Surface non-planarity or particulate matter on the wafer surface can lead to feature registration issues, when the components on adjacent layers do not xe2x80x9cline upxe2x80x9d properly, potentially leading to nonfunctional or faulty integrated circuits.
A primary challenge in wafer fabrication is the continuing reduction of defect levels. Defects potentially present on wafer surfaces include CMP slurry residue, oxides, organic contaminants, mobile ions and metallic impurities. Generally, a xe2x80x9ckiller defectxe2x80x9d (particle) can be as small as half the size of the device linewidth. For instance, a device using 0.18-micron (xcexcm) linewidth geometry will require that the wafer be substantially free of particles as small as 0.09 xcexcm, and at 0.13 xcexcm geometry, particles as small as 0.065 xcexcm. Due to their smaller size, it is physically more difficult to remove smaller particles than larger particles, so it is beneficial to prevent deposition of particles onto the wafers as much as possible.
Increasingly complex integrated circuits utilize an increasing number of circuit elements, which in turn requires both more electrical conduction paths between circuit elements and a greater number of conductor-insulator layers to achieve these paths. This has proved problematic for several reasons. First, longer interconnect paths means increasing resistance and capacitance, which not only decreases circuit speed by increasing RC-delay times but also increases resistive power loss. Second, an increasing number of layers makes successive layer-to-layer alignment, or registration, more difficult. Layers that lack global and local planarity further compound the registration problem. Historically, the techniques available to improve layer planarity in the semiconductor industry have been quite limited.
Until recently, aluminum was the interconnect conductor of choice in integrated circuit fabrication. Techniques for depositing thin aluminum films are well established and, because aluminum trichloride is somewhat volatile, aluminum can be etched effectively in chlorine plasmas to form patterned aluminum films following appropriate photolithography steps. At the same time, aluminum interconnects have several undesirable properties. First, aluminum is not an exceptionally good conductor; its resistivity is considerably higher than some other metals. Second, aluminum is particularly susceptible to electromigration, the physical movement of a conductor due to electron flow. Electromigration at grain boundaries results in conductor discontinuities and reduced circuit reliability.
The semiconductor industry is transitioning from aluminum to copper as the electrical conductor of choice for establishing interconnections between circuit elements. Copper has a significantly higher conductivity than aluminum and is inherently more resistant to electromigration. Although these properties of copper have been known for a long time, the absence of acceptable methods for selectively etching or otherwise removing copper have limited its use. Unlike aluminum, copper is not amenable to plasma etch. Thus, a key limitation in moving to copper metallization is the ability to etch or otherwise remove copper at the wafer surface. Improved CMP technologies are facilitating the shift to copper metallization, as CMP not only provides a method for copper removal and for forming patterned copper films, but also addresses the increased need for local and global planarity in complex integrated circuit architectures.
Today, CMP is an essential step in the manufacture of almost every modern integrated circuit. According to the 1997 National Technology Roadmap for Semiconductors, the typical logic device in 2004 will include seven inner-layer dielectric (ILD) CMP steps, seven metal CMP steps and one shallow trench isolation (STI) CMP step. Put simply, CMP is quickly becoming a central aspect of semiconductor processing in the formation of integrated circuits.
The CMP operation generally serves to remove excess coating material, reduce wafer topographical imperfections, and improve the depth of focus for photolithography processes through better planarity. The CMP process involves the controlled removal of material on the wafer surface through the combined chemical and mechanical action on the semiconductor wafer of a slurry of abrasive particles and a polishing pad. During the CMP operation, sub-micron-size particles from the associated polishing slurry are used to remove non-planar topographical features and extra coating on the wafer surface. After the CMP operation, these ultra-small slurry particles, typically silica (SiO2) or alumina (Al2O3), and particles from the polishing pad and polished wafer may remain on the wafer surface and can be problematic.
Following the CMP process, wafers are typically subjected to a post-CMP cleaning process to remove particulate and molecular contaminants before continuing the construction of the integrated circuit. For wafers processed in batches, rather than individually, storage techniques are used following the CMP process and prior to the post-CMP cleaning process. Storing the wafers frequently consists of placing them in a cassette filled with an appropriate liquid such as water.
For a variety of reasons, currently available CMP techniques are less than optimal. First, the CMP process involves the use of small, abrasive particles that can prove difficult to remove from the wafer surface. Although the slurry particles serve a valuable role during CMP, they constitute particulate defects following the CMP process. Consequently, techniques for improving the removal efficiency of slurry particles are desirable. In addition, molecular contaminants can be introduced during the CMP process that are not always effectively removed during post-CMP cleaning.
For batch-processed wafers, the wafer storage process can introduce additional problems. It has been noted that wafers removed from storage solutions can evidence streaking wherein contaminants appear preconcentrated in certain areas on the wafer surface. Furthermore, exposed copper surfaces are susceptible to corrosion, resulting in undesirable etching during the post-CMP storage and cleaning processes as well as potential electrical failure.
Defect levels on semiconductor wafers are closely monitored after several operations in the wafer fabrication process. One effective and quick way of measuring defect levels is to subject a wafer to a surface scanning process, which detects surface irregularities and particulate contamination with beams of laser light. As the CMP process is now widely used to provide global planarity of layers during wafer fabrication, successful yield management of CMP requires detection of critical defects such as non-uniform film thickness or process variations within a wafer lot. CMP defects can generally be separated into two categories: residual slurry particles or other foreign material on the wafer surface, and scratches, grooves or pits in the wafer surface itself. Both defect types are known to have a negative impact on device yield.
As is it often difficult to remove minute particles from the surfaces of wafers, new methods for reducing particulate contamination and buildup are always sought. Not only can particles cause killer defects by their very presence, they may also contribute to wafer surface damage, such as the aforementioned scratches, during subsequent post-CMP cleaning operations. Wafer surface damage can exacerbate particle removal difficulties, as particulate matter may become entrapped in grooved or scratched wafer surfaces. The shortcomings of the conventional CMP method become apparent during post-CMP defect detection, as defect levels are generally higher than desired. Consequently, it is desired to reduce defect levels on the polishing pad and head before polishing a wafer. It is further desired to develop a CMP method that reduces the possibility for particulate build-up between wafer polishing operations.
The preferred embodiments of the present invention include improved methods and compositions for chemical mechanical polishing (CMP) of a semiconductor wafer. The present invention teaches a CMP process further including the preconditioning steps of applying a cleaning chemistry to a polishing pad, contacting the polishing pad with a retaining ring, polishing the retaining ring and polishing pad with the cleaning chemistry, and removing the cleaning chemistry from the polishing pad. In a preferred embodiment, the cleaning chemistry comprises an aqueous solution between about 5 percent by weight and about 40 percent by weight of ammonium citrate, and preferably about 25 percent by weight of ammonium citrate. In an alternative embodiment, ascorbic acid, citric acid or other citric-based solutions having a relatively low pH may be used. Alternatively, cleaning chemistries with relatively high pH values, such as tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH), may be most effective at removing other types of slurries.
Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, semiconductor companies may refer to processes, components, and sub-components by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms xe2x80x9cincludingxe2x80x9d and xe2x80x9ccomprisingxe2x80x9d are used in an open-ended fashion, and thus should be interpreted to mean xe2x80x9cincluding, but not limited to . . . . xe2x80x9d
The term xe2x80x9csemiconductor devicexe2x80x9d refers generically to an integrated circuit, which includes internal electrical circuit elements and is fabricated upon a semiconductor substrate. A semiconductor device may be integral to a wafer, singulated from a wafer, or packaged for use on a circuit board. The term xe2x80x9cintegrated circuitxe2x80x9d refers to a semiconductor device. The term xe2x80x9ccircuit elementxe2x80x9d refers to the individual electrical components comprising an integrated circuit, including transistors, resistors and capacitors. The term xe2x80x9cdiexe2x80x9d refers generically to one or more integrated circuits, in various stages of completion, whether integral to a wafer or singulated from the wafer. The term xe2x80x9cwaferxe2x80x9d refers to a generally round, single-crystal semiconductor substrate upon which integrated circuits are fabricated in the form of die.
To the extent that any term is not specially defined in this specification, the intent is that the term is to be given its plain and ordinary meaning.